(1) Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device having a pattern of arrangement of elements which reduces the pitch of bit lines.
(2) Description of the Prior Art
In a semiconductor memory device, a plurality of word lines and bit lines are arranged perpendicular to each other. Memory cells are located at the cross positions of each word line and bit line. Each word line is connected to a row decoder circuit. Each bit line is connected to a sense amplifier circuit through a bit line selection transistor. The gate of each bit line selection transistor is connected to a column decoder circuit.
Recent demand for higher density integration semiconductor memory devices has necessitated denser patterns of arrangement of word lines and bit lines. To achieve denser patterns of arrangement of bit lines, it is necessary to reduce the pitch between bit lines. To reduce the pitch between bit lines, it is necessary to reduce the space between bit line selection transistors associated with the bit lines.